Exploiting high-level descriptions for circuits fault tolerance assessments

The paper proposes a new approach to estimate early the fault detection capability of a safety-critical computer-based system from its high-level description. This paper first aims at verifying the correspondence between dependability measures obtained through simulation-based fault injection experiments at different levels of abstraction. Then, we propose Alternative Graphs (AGs) to create lists of malicious faults without expanding the full data flow, whose size can often explode. Fault trees are exploited to improve the results of the high-level fault analysis. To evaluate the effectiveness of the approach, simulation-based fault injection experiments have been done on some benchmark systems described in VHDL language. The approach demonstrates that fault detection analysis performed at a high-level is less CPU time demanding but approximates well the fault detection measures achievable on a low-level system description