Title :
Total dose radiation response of a 45nm SOI Technology
Author :
Liu, S.T. ; Hurst, A. ; Hughes, H.L. ; McMarr, P. ; Benedito, J. ; Capasso, C.
Author_Institution :
TRUSTED Semicond. Solutions, Anoka, MN, USA
Abstract :
Partially depleted (PD) SOI CMOS technology has advanced from a small radiation hard niche market in the past to present main stream commercial applications because of advantages relative to device isolation and single event upset mitigation [1]. This paper is to investigate and present how the core 45nm SOI devices would behave in the total dose ionizing dose (TID) environment using a laboratory cobalt-60 radiation source under various irradiation biases. Individual NMOS transistors and arrays are packaged for testing. Since the individual transistors are not ESD protected, large yield loss was experienced in packaging by the conventional bonding techniques.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; isolation technology; radiation effects; silicon-on-insulator; ESD protected; NMOS transistors; SOI devices; SOI technology; TID environment; conventional bonding techniques; device isolation; dose radiation response; irradiation biases; laboratory cobalt-60 radiation source; partially depleted SOI CMOS technology; radiation hard niche market; single event upset mitigation; size 45 nm; total dose ionizing dose environment; yield loss; Logic gates; MOSFETs; Radiation effects; Silicon; Threshold voltage;
Conference_Titel :
SOI Conference (SOI), 2010 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-9130-8
Electronic_ISBN :
1078-621x
DOI :
10.1109/SOI.2010.5641052
