Author :
Liu, Y.X. ; Sekigawa, T. ; Hayashida, T. ; Matsukawa, T. ; Endo, K. ; O´uchi, S. ; Sakamoto, K. ; Ishii, K. ; Tsukada, T. ; Ishikawa, Y. ; Yamauchi, H. ; Ogura, A. ; Koike, H. ; Suzuki, E. ; Masahara, M.
Abstract :
The logic gate threshold voltage controllable single metal gate FinFET CMOS inverter constructed by the 3T-PMOS and 4T-NMOS have successfully been fabricated. The accurate current matching and the logic gate threshold voltage tuning by Vg2 in the 4T-NMOS have been demonstrated. A higher WF metal would be more suitable for the proposed FinFET CMOS.
Keywords :
CMOS logic circuits; MOSFET; etching; invertors; voltage control; 3T-PMOS; 4T-NMOS; logic gate threshold voltage; single metal gate FinFET CMOS inverters; wet etching; CMOS logic circuits; CMOS technology; Fabrication; FinFETs; Logic gates; MOS devices; Pulse inverters; Threshold voltage; Tin; Voltage control;
