Title :
A single-chip 16-bit 25 ns realtime video/image signal processor
Author :
Kikuchi, K. ; Nukada, Y. ; Aoki, Y. ; Kanou, T. ; Endo, Y. ; Nishitani, T.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
A single-chip real-time video/image processor (VISP) has been developed that integrates functions based on a variable seven-stage pipeline arithmetic architecture in a 16-bit fixed-point data format. A three-input adder implemented in complementary CMOS reduced-swing logic, which is twice as fast as conventional CMOS logic, achieving a 25-ns instruction cycle, is shown. Single-VISP processing times are: edge detection (3*3 Laplacian), 14.8 ms; distance calculation, 1.7 ms; temporal filtering (1-tap IR), 5.0 ms; linear quantization, 3.3 ms; and 3/5*3/5 picture reduction (separate 5-tap FIR), 5.9 ms. An example is shown of a two-dimensional discrete cosine transformation which requires 26.3 ms to execute with one VISP when 256*256 pixel processing at a 25-ns instruction cycle is employed.<>
Keywords :
CMOS integrated circuits; computerised picture processing; digital signal processing chips; pipeline processing; real-time systems; telecommunications computing; video equipment; video signals; 16 bit; 25 ns; 256 pixel; 65536 pixel; DSP chip; complementary CMOS reduced-swing logic; distance calculation; edge detection; fixed-point data format; instruction cycle; linear quantization; picture reduction; real-time; single-chip; temporal filtering; three-input adder; two-dimensional discrete cosine transformation; variable seven-stage pipeline arithmetic architecture; video/image processor; CMOS logic circuits; Filtering; Finite impulse response filter; Fixed-point arithmetic; Image edge detection; Laplace equations; Nonlinear filters; Pipelines; Quantization; Signal processing;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48246
