A highly-parallel VLSI architecture for a list sphere detector

Author

Widdup, Benjamin ; Woodward, Graeme ; Knagge, Geoff

Author_Institution

Wireless Networks Group & Bell Laboratories Res., Lucent Technol., North Ryde, NSW, Australia

Volume

5

fYear

2004

fDate

20-24 June 2004

Firstpage

2720

Abstract

Finding the nearest point in a lattice is an NP-hard problem for which we desire a simplified architecture. Furthermore, output of confidence measures or soft information is desirable for decoding/detection problems, yet generating such information further complicates the task. This paper presents an efficient and highly parallelisable architecture for a list sphere detector that is particularly suited to ASIC implementation. Various degrees of parallelism are explored and compared. This architecture finds application in multiuser and MIMO detectors, providing soft estimates of the transmitted symbols.

Keywords

MIMO systems; VLSI; application specific integrated circuits; computational complexity; decoding; multiuser detection; optimisation; ASIC implementation; MIMO detector; NP-hard problem; highly-parallel VLSI architecture; list sphere detector; multiuser detector; parallelisable architecture; Australia; Computer architecture; Detectors; Lattices; MIMO; Maximum likelihood decoding; Maximum likelihood detection; Maximum likelihood estimation; Multiuser detection; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2004 IEEE International Conference on

Print_ISBN

0-7803-8533-0

Type

conf

DOI

10.1109/ICC.2004.1313025

Filename

1313025