Title :
Optimization of low power quartermicron MOSFET
Author :
Min Cao ; Stork, H.
Author_Institution :
ULSI Res. Lab., Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
Both bulk and non-fully depleted silicon-on-insulator (NFD-SOI) 0.25 /spl mu/m MOSFETs have been systematically studied using analytical analysis and SPICE simulation. Energy*delay product is used in the analytical analysis for low power optimization. The results show that the optimal gate oxide thickness is determined by the sum of the junction capacitance and the interconnect capacitance, and the lower limit of the supply voltage is about 3Y/sub T/ because of the Y/sub T/ variation of the device. NFD-SOI devices have higher optimal gate oxide thickness and lower optimal V/sub DD//V/sub T/ ratio compared to bulk devices. The results also show that device scaling is the most effective way to reduce power dissipation without sacrificing speed, and NFD-SOI technology is attractive for low voltage and low power circuits.
Keywords :
CMOS integrated circuits; MOSFET; SPICE; minimisation; semiconductor device models; silicon-on-insulator; 0.25 mum; CMOS ring oscillators; MOSFET optimization; NFD-SOI devices; SPICE simulation; analytical analysis; device scaling; energy delay product; junction capacitance interconnect capacitance sum; low power 0.25 /spl mu/m MOSFET; low power optimization; low voltage low power circuits; nonfully depleted SOI MOSFET; optimal gate oxide thickness; power dissipation; supply voltage limit; Analytical models; Capacitance; Integrated circuit interconnections; MOSFET circuits; Power MOSFET; Power dissipation; Power system interconnection; SPICE; Silicon on insulator technology; Voltage;
Conference_Titel :
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-3036-6
DOI :
10.1109/LPE.1995.482474
