• DocumentCode
    316892
  • Title

    Study and realization of a novel high-voltage planar periphery [power semiconductor diodes]

  • Author

    Ngo, T. ; Schaeffer, Ch ; Guillemot, N. ; Arnould, J. ; Roux, L.

  • Author_Institution
    Fed. ELESA de INP de Grenoble, France
  • Volume
    2
  • fYear
    1997
  • fDate
    5-9 Oct 1997
  • Firstpage
    1006
  • Abstract
    A new methodology for designing a high voltage PLANAR periphery type single-pocket is presented in this paper. A geometry of the periphery type single-pocket which corresponds to the desired voltage-blocking capability characteristic can be obtained though this approach. The electric model presented can lead to a study of the electric field distribution in this periphery. The sensitivity of voltage-blocking capability of the periphery type single-pocket in relation to the implanted dose in the pocket was studied. Experimental results, which confirm the high sensitivity to the implanted dose are also presented. Based on this study, the authors developed the periphery type double-pocket in order to reduce this sensitivity and improve the breakdown voltage. The voltage-blocking capability of this structure is less sensitive to the implanted dose as compared to the structure single-pocket. An optimum structure double-pocket has been found for a given substrate. They have applied this periphery double-pocket to various power PIN silicon diodes with blocking voltages ranging from 2 kV to 3.5 kV. In all cases, they reached the ideal breakdown voltage for an abrupt one dimensional p-n junction
  • Keywords
    electric breakdown; p-i-n diodes; p-n junctions; power semiconductor diodes; semiconductor device models; semiconductor device testing; 2 to 3.5 kV; Si; breakdown voltage; electric field distribution; electric model; high-voltage planar periphery; implanted dose; one-dimensional p-n junction; p-i-n silicon diodes; periphery type double-pocket; power semiconductor diodes; substrate; voltage-blocking capability characteristic; Design methodology; Diodes; Doping; Electric variables; Geometry; Insulated gate bipolar transistors; Low voltage; Silicon; Space charge; Space technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industry Applications Conference, 1997. Thirty-Second IAS Annual Meeting, IAS '97., Conference Record of the 1997 IEEE
  • Conference_Location
    New Orleans, LA
  • ISSN
    0197-2618
  • Print_ISBN
    0-7803-4067-1
  • Type

    conf

  • DOI
    10.1109/IAS.1997.628984
  • Filename
    628984