Extraction of parasitic circuit elements in a PEBB for application in the virtual test bed

Author

Beker, Benjamin ; Hudgins, Jerry L. ; Coronati, John ; Gillett, Blake ; Shekhawat, Sampat

Author_Institution

Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA

Volume

2

fYear

1997

fDate

5-9 Oct 1997

Firstpage

1217

Abstract

A numerical procedure for extracting parasitic circuit elements using a quasi-static field solver, as part of the virtual test bed (VTB), is discussed. The parasitic inductance and capacitance values obtained from the model are compared to measured values from a low-inductance power electronic building block (PEBB) module, designed and constructed at Harris Semiconductor

Keywords

capacitance; circuit analysis computing; inductance; modules; power electronics; virtual reality; Harris Semiconductor; low-inductance; parasitic capacitance; parasitic circuit elements extraction; parasitic inductance; power electronic building block; quasi-static field solver; real time visualisation; virtual prototyping; virtual test bed; Application software; Circuit testing; Power electronics; Power system modeling; Power system simulation; Power system stability; Semiconductor device testing; System testing; Virtual prototyping; Visualization;

fLanguage

English

Publisher

ieee

Conference_Titel

Industry Applications Conference, 1997. Thirty-Second IAS Annual Meeting, IAS '97., Conference Record of the 1997 IEEE

Conference_Location

New Orleans, LA

ISSN

0197-2618

Print_ISBN

0-7803-4067-1

Type

conf

DOI

10.1109/IAS.1997.629015

Filename

629015