Title :
Analysis of effects of using exponent adders in IEEE-754 multiplier by VHDL
Author :
Parte, Ragini ; Jain, Jitendra
Author_Institution :
Dept. of Electron. & Commun. Engniering, Bansal Inst. of Sci. & Technol., Bhopal, India
Abstract :
Floating point arithmetic has a vast applications in DSP, digital computers, robots due to its ability to represent very small numbers and big numbers as well as signed numbers and unsigned numbers. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Here we analyze the effects of using three different types of adders while calculating the single precision and double precision floating point multiplication. We also present the multiplication of significand bits by decomposition of operands method for IEEE 754 standard.
Keywords :
IEEE standards; adders; carry logic; electronic engineering computing; floating point arithmetic; hardware description languages; multiplying circuits; IEEE 754 multiplier; MCPD; VHDL; carry select adder; carry skip adder; effect analysis; exponent adder; floating point arithmetic; floating point multiplication; maximum combination path delay; Adders; Computers; Delays; Field programmable gate arrays; Floating-point arithmetic; Logic gates; Standards; Double Precision Floating Point (DP FP); IEEE754; Maximum Combinational Path Delay (MCPD); Single Precision Floating Point (SP FP);
Conference_Titel :
Circuit, Power and Computing Technologies (ICCPCT), 2015 International Conference on
Conference_Location :
Nagercoil
DOI :
10.1109/ICCPCT.2015.7159292
