Title :
A CMOS sea-of-gates array with continuous track allocation
Author :
Okabe, M. ; Okuno, Y. ; Arakawa, T. ; Tomioka, I. ; Ohno, T. ; Noda, T. ; Hatanaka, M. ; Kuramitsu, Y.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A macrocell architecture which is suitable for sea-of-gates (SOG) arrays and improves gate density is described. A layout scheme using a novel structure called column macrocell (CMC) implements every macrocell by stacking BCs (basic cells) along the BC column until enough gates are accumulated. In the CMC structure, the first-level wiring runs along the BC column, and the wiring channel width can be adjusted by 1-2 tracks. Therefore just as many tracks as are necessary in a channel are produced by first-level wiring. The effectiveness of the CMC structure is verified by implementing an SOG chip using LDD (lightly doped drain) PMOS and NMOS transistors with 0.8- mu m physical and 0.55- mu m effective gate length. The features of the CMC structure are compared with those of the RMC (row macrocell) structure.<>
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; logic arrays; 0.55 micron; 0.8 micron; CMOS; LDD transistors; SOG; VLSI; column macrocell; continuous track allocation; gate length; layout scheme; lightly doped drain; logic arrays; macrocell architecture; sea-of-gates array; twin well structure; Delay; Laboratories; Large scale integration; Large-scale systems; Logic; Macrocell networks; Power distribution; Registers; Research and development; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48250
