Low phase noise S-band PLL frequency synthesizer using DDS and offset mixing techniques

Author

Choi, Jaehung ; Kim, Minsu ; Shin, Seungha ; Yang, Youngoo

Author_Institution

Sch. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea

fYear

2009

fDate

7-10 Dec. 2009

Firstpage

1409

Lastpage

1412

Abstract

The paper presents the design and implementation of a DDS-driven PLL frequency synthesizer module using an offset mixing technique. The DDS, which is adopted as the reference generation for the PLL synthesizer, allows the synthesizer to have a fast switching time and narrow channel spacing. The offset mixing method allows an excellent in-band phase noise feature. The implemented frequency synthesizer has an excellent phase noise of -91.6 dBc/Hz at an offset of 10 KHz for the center frequency of 4.6 GHz.

Keywords

direct digital synthesis; phase locked loops; DDS; channel spacing; direct digital frequency synthesizer; frequency 10 kHz; frequency 4.6 GHz; inband phase noise feature; low-phase noise S-band PLL frequency synthesizer; offset mixing method; offset mixing techniques; phase locked loops; Channel spacing; Circuit synthesis; Clocks; Frequency synthesizers; Phase locked loops; Phase noise; Signal generators; Signal synthesis; Switching converters; Table lookup; Direct Digital Frequency Synthesizer; Frequency Synthesizer; Offset Mixing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2009. APMC 2009. Asia Pacific

Conference_Location

Singapore

Print_ISBN

978-1-4244-2801-4

Electronic_ISBN

978-1-4244-2802-1

Type

conf

DOI

10.1109/APMC.2009.5384505

Filename

5384505