A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information

In this paper, a Nyquist ADC with a time-based pipelined TDC is proposed. In the proposed ADC, the first pipeline stage incorporates both residue amplification and a V-T conversion with high accuracy, efficiently realized by a low gain amplifier with only 24 dB dc gain. Furthermore, adding to power efficiency, a hybrid time-domain pipeline stage based on simple charge pump and capacitor DAC in its backend stages is also proposed. Using the right combination of voltage and time domain information, the proposed ADC architecture benefits from improved resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13 μm CMOS demonstrate peak SNDR of 69.3 dB at 6.38 mW power and 70 MHz sampling frequency. The FOM based on peak SNDR is 38.2 fJ/conversion-step.