DocumentCode :
3171167
Title :
Instruction prefetching using branch prediction information
Author :
Chen, I-Cheng K. ; Lee, Chih-Chieh ; Mudge, Trevor N.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear :
1997
fDate :
12-15 Oct 1997
Firstpage :
593
Lastpage :
601
Abstract :
Instruction prefetching can effectively reduce instruction cache misses, thus improving the performance. In this paper, we propose a prefetching scheme, which employs a branch predictor to run ahead of the execution unit and to prefetch potentially useful instructions. Branch prediction-based (BP-based) prefetching has a separate small fetching unit, allowing it to compute and predict targets autonomously. Our simulations show that a 4-issue machine with BP-based prefetching achieves higher performance than a plain cache 4 times the size. In addition, BP-based prefetching outperforms other hardware instruction fetching schemes, such as next-n line prefetching and wrong-path prefetching, by a factor of 17-44% in stall overhead
Keywords :
computer architecture; instruction sets; branch prediction information; branch predictor; hardware instruction fetching schemes; instruction cache misses; instruction prefetching; simulations; Accuracy; Analytical models; Computational modeling; Costs; Counting circuits; Delay; Hardware; Microprocessors; Prefetching; System performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-8206-X
Type :
conf
DOI :
10.1109/ICCD.1997.628926
Filename :
628926
Link To Document :
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