A processor architecture for ultra high-speed one-dimensional digital filtering

A high-performance VLSI architecture for one-dimensional digital filtering applications is presented. The development of the processor architecture is based upon an algorithm decomposition scheme which increases parallelism with minimum data communication requirements. This architecture uses multiple processing units in order to achieve very high throughput. The individual processors are programmable, which provides flexibility for a wide range of applications, and they can be cascaded to implement a very-high-order system. The computational structure, processor architecture, and system configuration are discussed