Title :
Synthesis of delay verifiable sequential circuits using partial enhanced scan
Author :
Takumalla, R.C. ; Menon, Prem R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The path delay fault testability of sequential circuits is limited by state transitions that can be produced during normal operation. As a result, there may be untestable faults some of which may affect circuit behavior. The authors first extend the concept of primitive faults to sequential circuits. They then describe a method of selecting a set of flip-flops for partial enhanced-scan, such that falling transitions on all paths are made robustly testable in a two-level prime and irredundant realization of the sequential circuit. It results in a robust or VNR test for every rising transition primitive fault, using the available state transitions. A method of synthesizing sequential circuits such that untestable faults do not affect the initialization, is presented. An area comparison between area-optimized and delay-verifiable versions of the MCNC ´91 benchmark circuits is also presented
Keywords :
delays; fault diagnosis; flip-flops; logic testing; sequential circuits; timing; VNR test; area-optimized MCNC ´91 benchmark circuits; circuit behavior; delay verifiable sequential circuit synthesis; delay-verifiable MCNC ´91 benchmark circuits; falling transitions; flip-flops; initialization; normal operation; partial enhanced scan; path delay fault testability; primitive faults; rising transition primitive fault; robust test; state transitions; untestable faults; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Delay; Flip-flops; Robustness; Sequential analysis; Sequential circuits;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-8206-X
DOI :
10.1109/ICCD.1997.628934
