Title :
A 23 ps/2.1 mW ECL gate
Author :
Toh, K.-Y. ; Chuang, C.-T. ; Chen, T.-C. ; Warnock, J. ; Li, G.-P. ; Chin, K. ; Ning, T.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Simulated output waveforms at 0.1, 0.3 and, 0.6-pF loading of a design optimized for a 0.3-pF nominal load are shown. An AC-coupled APD ECL (active-pull-down emitter-coupled-logic) gate with significantly improved gate delay in the low-power (1-2 mW) regime is described. Unloaded gate delays of 23 and 35 ps at 2.1 and 1.1-mW/gate power, respectively, were demonstrated in a bipolar technology using a double-poly, self-aligned process with emitter width of 0.8 mu m (mask). The device cross-section is presented along with an SEM (scanning electron microscopy) micrograph of the basic gate used in the ring oscillator.<>
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; logic gates; oscillators; 0.1 to 0.6 pF; 0.8 micron; 2.1 mW; 23 ps; AC-coupled APD ECL; ECL gate; SEM micrograph; active-pull-down; bipolar technology; device cross-section; double-poly; emitter width; emitter-coupled-logic; gate delay; output waveforms; ring oscillator; self-aligned process; Bipolar integrated circuits; Circuit simulation; Coupling circuits; Delay; Design optimization; Diodes; Resistors; Thermal resistance; Transient response; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48265
