Performance analysis of ATM switches with multistage multipath packet switching interconnection networks

Because of their ability of nonblocking and fault tolerance, multistage-multipath networks provide useful characteristics for ATM switches and large-scale parallel computers. In this paper an analytical model for the analysis of ATM switches based on multistage-multipath packet switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed model is general in that it analyzes ATM switches under uniform and nonuniform traffic. First, a general model of synchronous buffered switching element, using output buffering, under an assumption of finite buffer size for a very general class of traffic patterns, is presented. It is assumed that the subsequent stages of the network are nearly independent, and a model is extended for the entire network under this assumption. The analytical results obtained with the proposed model are then compared with the results obtained for single path networks, and it is shown that the model is general enough for the class of multipath networks