Effect of sample clock jitter on IF-sampling IS-95 receivers

The development of inexpensive, wideband, high dynamic range ADCs has made feasible a new class of receivers based on direct IF undersampling techniques. This type of receiver architecture is characterized by high intermediate frequencies (IFs), often in the 100-250 MHz range. At these IFs the conventional theory shows that for non-spread modulation schemes a small amount of sample clock jitter can lead to significant phase modulation of the desired signal thus limiting the SNR at the ADC output. Unfortunately, the same theory cannot be directly applied to spread spectrum (SS) systems in which the IF SNR is very low. This paper shows that, neglecting adjacent channel interference, the principal effect of sample clock jitter in direct-sequence SS receivers is to reduce chip coherency during despreading. Results are derived relating the loss of receiver performance to the IF frequency and the ADC sample clock single-sideband phase noise density to carrier ratio. These results are then used to define sample clock jitter requirements for an exemplary IS-95 IF-sampling receiver