Title :
A CMOS to 100 K ECL interface circuit
Author :
Pedersen, M. ; Metz, P.
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
The authors have designed and fabricated a true CMOS/ECL (emitter-coupled logic) interface in a 0.9- mu m CMOS technology. This interface requires only a single external reference resistor to be completely ECL 100 K compatible. It accepts as input AC- or DC-coupled, differential or single-ended ECL 100 K signals and outputs the same. The interface demonstrates 100-MHz single-ended and 200-MHz differential operation while maintaining true ECL output levels and is part of a monolithic 200-MHz clock recovery circuit. Interface circuit characteristics are listed, and a block diagram is presented.<>
Keywords :
CMOS integrated circuits; digital integrated circuits; emitter-coupled logic; integrated circuit technology; 0.9 micron; 100 MHz; 100 MHz single ended operation; 200 MHz; 200-MHz differential operation; CMOS to 100 K ECL interface circuit; ECL 100 K compatible; block diagram; characteristics; emitter-coupled logic; monolithic 200-MHz clock recovery circuit; single external reference resistor; true ECL output levels; CMOS technology; Circuits; Clocks; Dairy products; Feedback; Impedance; Inverters; Mirrors; Resistors; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48267
