DocumentCode :
31740
Title :
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance
Author :
Bowman, Keith A. ; Tokunaga, Carlos ; Karnik, T. ; De, Vivek K. ; Tschanz, James W.
Author_Institution :
Intel Corporation, Hillsboro, OR, USA
Volume :
48
Issue :
4
fYear :
2013
fDate :
Apr-13
Firstpage :
907
Lastpage :
916
Abstract :
An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage ({\\rm V}_{{\\rm CC}}) droops on microprocessor performance and energy efficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in critical paths during a {\\rm V}_{{\\rm CC}} droop. The tunable-length delay prevents critical-path timing-margin degradation for multiple cycles after the {\\rm V}_{{\\rm CC}} droop occurs, thus allowing a sufficient response time for dynamic adaptation. An on-die dynamic variation monitor detects the onset of the {\\rm V}_{{\\rm CC}} droop to proactively gate the clock at the end of the tunable-length delay to eliminate the clock edges that would otherwise degrade critical-path timing margin. In comparison to a conventional clock distribution, silicon measurements from a 22 nm test chip demonstrate simultaneous throughput gains and energy reductions of 14% and 3% at 1.0 V, 18% and 5% at 0.8 V, and 31% and 15% at 0.6 V, respectively, for a 10% {\\rm V}_{{\\rm CC}} droop.
Keywords :
Clocks; Delay; Microprocessors; Pipelines; Sensitivity; Transistors; Adaptive circuit; adaptive clocking; adaptive design; clock-data compensation; resilient circuit; resilient design; variation tolerance; variation-tolerant design; voltage droop; voltage variation;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2013.2237972
Filename :
6422331
Link To Document :
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