Title :
A 25 ns 4 Mb CMOS SRAM with dynamic bit line loads
Author :
Miyaji, F. ; Matsuyama, Y. ; Naiki, I. ; Takahashi, H. ; Sasaki, M. ; Takeda, M. ; Sugano, Y. ; Hagiwara, Y. ; Nishiyama, K. ; Tsumori, T. ; Kobayashi, K. ; Hirano, K. ; Shimada, T.
Author_Institution :
SONY, Kanagawa, Japan
Abstract :
A 4-Mb CMOS SRAM (static RAM) with an access time of 25 ns designed for a single 3.3-V supply voltage and a 400-mil DIP (dual-in-line) package, using a 0.5- mu m double-polysilicon and double-aluminum CMOS technology, is presented. A 25-ns address access time was achieved by a dynamic bit-line-load circuit scheme combined with an address transition detector (ATD), divided word line structure, and three-stage sense amplifier approach. The hierarchical structure of the memory cell array with 512-kw*8-b organization is shown. Active operating currents of 33 mA and 46 mA have been obtained at 10 MHz and 40 MHz, respectively. A standby current of 70 mu A has been realized at V/sub cc/=3.3 V and V/sub IH/=2.2 V. The RAM output waveforms for address access with 30-pF load capacitance are shown. The characteristics of the RAM are summarized.<>
Keywords :
CMOS integrated circuits; VLSI; integrated memory circuits; random-access storage; 0.5 micron; 10 MHz; 25 ns; 33 mA; 4 Mbit; 40 MHz; 46 mA; CMOS SRAM; CMOS technology; DIP; access time; address transition detector; dynamic bit line loads; dynamic bit-line-load circuit scheme; hierarchical structure; operating currents; output waveforms; supply voltage; three-stage sense amplifier approach; Aluminum; CMOS technology; Capacitance; Circuits; Delay; MOSFETs; Random access memory; Read-write memory; Research and development; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48277
