CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits

Despite the potential benefits of asynchronous circuits compared to synchronous circuits, only small advances have been made in the adaptation of asynchronous methodologies by the electronics industry. One of the most important reasons for that, is the lack of asynchronous Electronic Design Automation (EDA) tools and the fact that existing EDA tools are not suitable for asynchronous implementations. Moreover, physical EDA tools, like placement algorithms, involve methodologies which are not applicable to asynchronous circuits, such as static timing analysis (STA) which cannot be performed in a cyclic circuit. In this work, we present CPlace, a constructive placement algorithm which can efficiently handle asynchronous circuits. We use timing separation of events for timing analysis and maintain the quasi-delay insensitive (QDI) properties by bounding the relative delays of wires in isochronic forks. We employ absolute timing constraints for performance and relative timing constraints for QDI which are handled by an ILP formulation. Experimental results show the effectiveness of CPlace in respecting QDI constraints against a synchronous, state-of-the-art industrial placer and a well-known academic placer.