DocumentCode :
3175788
Title :
An alternative approach to backside via reveal (BVR) for a via-middle through-Silicon via (TSV) flow
Author :
Jengyi Yu ; Detterbeck, Stefan ; CheePing Lee ; Meshram, Prashant ; Mountsier, Tom ; Lai Wei ; Qing Xu ; Gopinath, Sanjay ; Nalla, Praveen ; Thorum, Matthew ; Richardson, Joe
Author_Institution :
Lam Res. Corp, Fremont, CA, USA
fYear :
2015
fDate :
26-29 May 2015
Firstpage :
551
Lastpage :
554
Abstract :
An alternative scheme has been developed to combine three major backside via reveal (BVR) processes, including (a) wafer polishing, (b) Si recess etching, and (c) wet clean, into an integrated wet etch process to replace the high cost chemical-mechanical planarization (CMP) and dry etching steps. The process combines two steps on a single-wafer platform: (1) bulk Si etching chemistry with high etch rate (>10 μm/min.) to replace the CMP or polishing and (2) selective Si etching chemistry (Si: SiO2 ~ 1800:1) to replace the Si recess dry etching step. Using this process, Si thickness uniformity can be significantly improved (for 20 μm Si removal), resulting in a lower variation in step height of through-Si via (TSV) protrusion across a 300 mm wafer. The overall cost is significantly lower than CMP plus dry etching. After the integrated wet etching process, passivation layers of low-temperature silicon nitride and oxide were deposited on the backside, followed by CMP to planarize the wafer and expose the Cu nails. The film adhesion is very good without showing any film delamination or peeling. This new integration scheme is robust with a wide process margin and provides cost savings over the conventional BVR flow.
Keywords :
etching; polishing; surface cleaning; three-dimensional integrated circuits; backside via reveal; chemical mechanical planarization replacement; dry etching replacement; integrated wet etch process; recess etching; selective etching chemistry; size 300 mm; via middle through silicon via flow; wafer polishing; wet clean; Etching; Kelvin; Passivation; Planarization; Resistance; Silicon; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/ECTC.2015.7159644
Filename :
7159644
Link To Document :
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