Title :
Present ability and problems of ultra-shallow junction formation by RTA
Author :
Matsuda, T. ; Shishiguchi, S. ; Kitajima, H.
Author_Institution :
USLI Device Dev. Div., NEC Corp., Kanagawa, Japan
Abstract :
This article describes the current capability and problems in ultra-shallow junction formation by using rapid thermal annealing (RTA). By using this technology, shallow junctions with low sheet-resistance and good process controllability for early 100 nm technology nodes can be achieved, even though problems remain with process controllability for wafers of various structures and with the transient-enhanced diffusion (TED) effect of gate side-wall spacers.
Keywords :
doping profiles; electric resistance; integrated circuit technology; process control; rapid thermal annealing; semiconductor technology; 100 nm; RTA; gate side-wall spacers; process controllability; rapid thermal annealing; shallow junction technology; sheet-resistance; technology nodes; transient-enhanced diffusion; ultra-shallow junction formation; wafer structures; Boron; CMOS technology; Controllability; Implants; National electric code; Rapid thermal annealing; Rapid thermal processing; Space technology; Temperature distribution; Ultra large scale integration;
Conference_Titel :
Junction Technology, 2000, The first international workshop on, Extended abstracts of
Conference_Location :
Makuhari, Japan
Print_ISBN :
4-89114-008-9
DOI :
10.1109/IWIT.2000.928773
