Challenges of flip chip packaging with embedded fine line and multi-layer coreless substrate

As mobile electronics are continuously driven for compact, slim and lightweight, miniaturization of IC packaging has been a must. Coreless substrate with fine-trace embedded technology is a key to achieve package miniaturization. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layers to interconnect the chip and the PCB board. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. Therefore, as a NEW innovative coreless structure, a substrate with the features of embedded trace has aroused lots of attention in IC semiconductor industry. Its trace is plated on a flat carrier and is embedded just after the plating. By using this unique embedded trace technology, it makes the fine-line of having 20um/20um or 15um/15um line width/space and having no concern for high cost. Without rigid core layer, the major challenges of this coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage during substrate manufacturing, prepreg (PP) was employed as the dielectric layer of a substrate. Furthermore the glass fiber in PP can reinforce the rigidity and flatness. For assembly process, lots of experiments were conducted extensively to reduce the package warpage, including molding compound selection (which focus on its CTE and Tg adjustments), post-mold cure optimization, die thickness decision, and so on. In this paper, a test vehicle (flip-chip package, 12x12mm2 body size, above 500 IO count) was carried out. 2layer and 3layer substrates were built for the different applications and were evaluated. Stress simulation was conducted to determine the package structure and work out the bill of material. Screen and corner DOEs which includes molding compound selection, die-bond reflow profile and post-mold cure para- eters were performed to come out the optimal material and process window. Reliability and functional test have been passed as well. Hence coreless substrate with embedded trace technology has been proven to be a feasible and reliable way for the miniaturization in assembly industry.