Title :
On the design of constant weight codes for VLSI systems
Author :
Tallini, L.G. ; Bose, B.
Author_Institution :
Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Abstract :
A constant weight, w, code with k information bits and r check bits is a binary code of length n=k+r and cardinality 2/sup k/ such that the number of 1s in each code word is equal to w. When w=~n/2 the code is called balanced. The paper describes the design of constant weight codes with parallel encoding and parallel decoding. Infinite families of efficient constant weight codes are given with the parameters k, r and the "number of balancing functions used in the code design", p. The larger p grows the smaller r will be; and the codes can be encoded and decoded with VLSI circuits whose sizes and depths are proportional to pk and log/sub 2/p respectively. For example, a design is given for a constant weight w=33 code with k=64 information bits, r=10 check bits and p=8 balancing functions. This code can be implemented by a VLSI circuit using less than 4054 transistors with a depth of less than 30 transistors.
Keywords :
VLSI; combinational circuits; concatenated codes; decoding; digital integrated circuits; encoding; integrated circuit design; parallel processing; VLSI circuits; VLSI systems; balanced code; balancing functions; binary code; cardinality; check bits; constant weight code design; information bits; parallel decoding; parallel encoding; transistors; Binary codes; Combinational circuits; Computer science; Decoding; Design methodology; Encoding; Error correction codes; Noise reduction; Redundancy; Very large scale integration;
Conference_Titel :
Fault-Tolerant Computing, 1997. FTCS-27. Digest of Papers., Twenty-Seventh Annual International Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-8186-7831-3
DOI :
10.1109/FTCS.1997.614095