Title :
A 90 nm low-power successive approximation register for A/D conversions
Author :
Shaker, Mohamed O. ; Bayoumi, Magdy A.
Author_Institution :
Univ. of Louisiana at Lafayette, Lafayette, LA, USA
Abstract :
A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 14 bits has been designed up to the layout level with 1V power supply in 90nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption and 18% of transistor count.
Keywords :
CMOS logic circuits; analogue-digital conversion; circuit simulation; clocks; integrated circuit layout; low-power electronics; A/D conversion; CMOS technology; SPECTRE simulation; circuit layout; clock gating; low-power successive approximation register; power consumption; power supply; size 90 nm; transistor count; word length 14 bit; Approximation methods; CMOS integrated circuits; Clocks; Logic gates; Power demand; Registers; Transistors; Low power; clock gating; layout simulations; successive approximation register;
Conference_Titel :
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-61284-913-3
DOI :
10.1109/ISQED.2011.5770742
