Delay optimization considering power saving in dynamic CMOS circuits

Performance variation is one of the primary concerns in nanometer-scale dynamic CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware Transistor (PVT) sizing algorithm is proposed, which is capable of significantly reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in dynamic CMOS circuits. The proposed algorithm is based on identifying the significance of all timing paths in the design, increasing the sizes of transistors that appear in most number of paths to reduce delays of most paths. In parallel, it minimizes the channel load by reducing the size of transistors in the interacting paths, which will lead to a power saving. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.