Void-effect modeling of flip-chip encapsulation on ceramic substrate

Author

Niu, Tyan-Min ; Sammakia, Bahgat ; Sathe, Sanjeev

Author_Institution

IBM Corp., Endicott, NY, USA

fYear

1998

fDate

27-30 May 1998

Firstpage

251

Lastpage

255

Abstract

A detailed numerical and experimental study of the thermal-mechanical stress and strain in the C4 solder bumps of a flip chip ceramic chip carrier has been completed. The numerical model used was based upon the finite element method. The model simulated accelerated thermal cycling (ATC) from 0°C to 100°C. Several parametric studies were conducted, including the effects of chip size, micro-encapsulation, and the effect of the presence of voids in the micro-encapsulant. It was notably found that the presence of voids in the encapsulant does not significantly increase the stress/strain in the C4s, with the exception of very large voids and voids at or near the edge of the chip

Keywords

ceramic packaging; encapsulation; finite element analysis; flip-chip devices; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; stress-strain relations; thermal stresses; voids (solid); 0 to 100 C; C4 solder bumps; C4 stress/strain; accelerated thermal cycling simulation; ceramic substrate; chip edge voids; chip size; finite element method; flip chip ceramic chip carrier; flip-chip encapsulation; micro-encapsulant voids; micro-encapsulation; numerical model; thermal-mechanical strain; thermal-mechanical stress; void size; void-effect modeling; Capacitive sensors; Ceramics; Electronics packaging; Encapsulation; Fatigue; Finite element methods; Metallization; Temperature; Testing; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal and Thermomechanical Phenomena in Electronic Systems, 1998. ITHERM '98. The Sixth Intersociety Conference on

Conference_Location

Seattle, WA

ISSN

1089-9870

Print_ISBN

0-7803-4475-8

Type

conf

DOI

10.1109/ITHERM.1998.689555

Filename

689555