Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs

High-level synthesis (HLS) for FPGA designs has received considerable attention in recent years. To make this design methodology mainstream, improved debugging technologies are essential. Ideally, a user should be able to debug their design using the original source code, without detailed knowledge of the underlying hardware, while the circuit executes in-situ. Although recent work has made progress toward this goal, existing solutions are unable to provide visibility into circuits that have been heavily optimized by the compiler. HLS compilers typically perform many optimizations, including moving variable values out of memories and into registers distributed throughout the design. Debugging such circuits typically requires either understanding the hardware and probing the appropriate RTL level registers, or ignoring these variables while debugging the design, neither of which is desirable. In this work we present a new signal-tracing technique, specifically designed for circuits that have been optimized by an HLS tool. Information is extracted from the HLS process to determine which signals are relevant to record each cycle. We automatically embed circuitry which dynamically selects the relevant signals, cycle-by-cycle, and records them into on-chip memories. In addition, we explore techniques to balance tracing between cycles to further improve memory efficiency. For each 100Kb of memory allocated to trace buffers, our technique can, on average, record and replay 4322 lines of source code, versus 141 lines using traditional tracing methods.