An Efficient Hardware Simulator for the Design of a WCDMA Interference Cancellation Repeater

An efficient hardware simulator for the design of a WCDMA interference cancellation repeater (ICR) is presented. The ICR, which is composed of a digital interference canceller and analog parts, is a time-varying system that reacts to a time varying input signal. The design of the digital interference canceller is time-consuming due to the need for many iteration cycles of debugging, tuning, and performance verification. Furthermore, its performance, which is represented by the error vector magnitude (EVM) and the output power spectrum, can be verified only after it is implemented on a digital board, integrated into the repeater hardware with analog parts, and hooked up with expensive test equipment. Hence, a special computerized simulator is needed for fast and efficient verification of the interference canceller´s design. The simulator consists of a signal generator, which emulates a base station, the ICR with an interference canceller, a feedback channel that models wireless fading channels, and a receiver that measures the EVM of the ICR. The accuracy of the simulator is verified by showing that the EVM and the output power spectrum of a reference interference canceller measured on this simulator match well within an error range of less than 8% with the corresponding values measured on the repeater hardware. The usefulness of the simulator is also confirmed by simulating the EVM performance of the ICR under various multipath fading channel conditions.