Title :
Power Integrity in Silicon-Package-Board Codesign Flow
Author_Institution :
Cadence Design Syst., Inc., Shanghai
Abstract :
This paper introduces a process that allows customers to import current profiles from IC tools like VoltageStorm at Cadence, package models obtained from field solver and on-die capacitance to be simulated together. The users can view the impedance in frequency domain and voltage ripples in time domain.
Keywords :
capacitance; elemental semiconductors; frequency-domain analysis; integrated circuit design; integrated circuit packaging; silicon; time-domain analysis; Cadence; IC-package-board codesign flow; Si; VoltageStorm; field solver; frequency domain; on-die capacitance; power integrity analysis; silicon-package-board codesign flow; time domain; voltage ripples; Frequency domain analysis; Impedance; Integrated circuit modeling; Integrated circuit noise; Integrated circuit packaging; Pins; Power system interconnection; Power system modeling; Signal design; Voltage;
Conference_Titel :
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-1253-6
Electronic_ISBN :
1-4244-1253-6
DOI :
10.1109/HDP.2007.4283601
