Title :
LV∗: A low complexity lazy versioning HTM infrastructure
Author :
Negi, Anurag ; Waliullah, M.M. ; Stenstrom, Per
Author_Institution :
Dept. of Comput. Sci. & Eng., Chalmers Univ. of Technol., Gothenburg, Sweden
Abstract :
Transactional memory (TM) promises to unlock parallelism in software in a safer and easier way than lock-based approaches but the path to deployment is unclear for several reasons. First of all, since TM has not been deployed in any machine yet, experience of using it is limited. While software transactional memory implementations exist, they are too slow to provide useful experience. Existing hardware transactional memory implementations, on the other hand, can provide the efficiency required but they require a significant effort to integrate in cache coherence infrastructures or freeze critical policy parameters. This paper proposes the LV* (lazy versioning and eager/lazy conflict resolution) class of hardware transactional memory protocols. This class of protocols has been implemented with ease of deployment in mind. LV* can be integrated with low additional complexity in standard snoopy-cache MESI-protocols and can be accommodated in a directory-based cache coherence infrastructure. Since the optimal conflict resolution policy (lazy or eager) depends on transactional characteristics of workloads, LV* supports a set of conflict resolution policies that range from LazEr - a family of Lazy versioning Eager conflict resolution protocols - to LL-MESI which provides lazy resolution. We show that LV* can be hosted in a MESI protocol through straightforward extensions and that the flexibility in the choice of conflict resolution strategy has a significant impact on performance.
Keywords :
cache storage; memory architecture; parallel architectures; parallelising compilers; protocols; LL-MESI; LV; LazEr; directory-based cache coherence infrastructure; hardware transactional memory protocol; lazy versioning eager conflict resolution protocol; lock-based approach; low complexity lazy versioning HTM infrastructure; parallel architecture; snoopy-cache MESI-protocol; software parallelism; software transactional memory; Coherence; Complexity theory; Hardware; Multicore processing; Protocols; Software; Strontium; Hardware; Memory; Parallel Architectures; Transactional;
Conference_Titel :
Embedded Computer Systems (SAMOS), 2010 International Conference on
Conference_Location :
Samos
Print_ISBN :
978-1-4244-7936-8
Electronic_ISBN :
978-1-4244-7938-2
DOI :
10.1109/ICSAMOS.2010.5642062