DocumentCode
318406
Title
Scan latch design for delay test
Author
Savir, Jacob
Author_Institution
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fYear
1997
fDate
1-6 Nov 1997
Firstpage
446
Lastpage
453
Abstract
This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips
Keywords
built-in self test; combinational circuits; delays; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; random processes; shift registers; AC fault coverage; BIST; DC fault coverage; LFSR; LSSD; MISR; SRL; chip overhead; cost; delay test; distributed self-test; level sensitive scan design; pilot chips; scan latch design; shift register latch; test vectors; Built-in self-test; Circuit faults; Circuit testing; Costs; Delay; Design for testability; Hardware; Latches; Protocols; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1997. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-4209-7
Type
conf
DOI
10.1109/TEST.1997.639650
Filename
639650
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