Design of a flexible high-speed FPGA-based flow monitor for next generation networks

The evolution of new services and the development of next generation networks is placing severe demands on networks. In order to support emerging services, it is clear that a higher degree of monitoring functionality is needed within networks. One approach is to use the programmability and performance of Field Programmable Gate Array (FPGA) technology to allow distributed monitoring but this present challenges around memory usage and highlights the need for a strategically different approach to how flows are monitored. A novel FPGA-based, programmable IP flow monitor is presented, that permits various forms of network monitoring functionality, specifically monitoring of different classes of traffic, to be performed. A key aspect was to address the traditionally long design times, through the use of a new, experimental, high-level design flow called Packet Xpress which allowed functions to be quickly implemented, providing a twentyfold speed-up in design time. The monitor has been implemented on a Xilinx Virtex-5 based ML506 board and verified in hardware using real Internet traffic traces. The platform allowed us to experiment with various monitoring functions and establish their resource requirements.