Automatic EB fault tracing system by successive circuit extraction from VLSI CAD layout data

Author

Miura, Katsuyoshi ; Nakata, Kohei ; Nakamae, Koji ; Fujioka, Hiromu

Author_Institution

Fac. of Eng., Osaka Univ., Japan

fYear

1997

fDate

17-19 Nov 1997

Firstpage

162

Lastpage

167

Abstract

An automatic electron beam (EB) fault tracing system is described which enables us to trace faults automatically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit independently of circuit functions. Only VLSI CAD layout data is required

Keywords

VLSI; automatic test equipment; automatic test software; circuit layout CAD; electron beam testing; fault location; integrated circuit testing; scanning electron microscopy; VLSI CAD layout data; automatic testing; electron beam fault tracing; transistor-level circuit; Circuit faults; Circuit testing; Data engineering; Data mining; Design automation; Large scale integration; Pins; Scanning electron microscopy; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643953

Filename

643953

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=318852