A novel FPGA architecture supporting wide shallow memories

This paper presents a novel architecture for on-chip user storage in a FPGA. Shallow wide memories are provided by allowing the user to write and read the configuration memory in unused switch blocks. Implementing this technique on a 100×100 logic block FPGA with 128 tracks per channel gives a total of 9.46 Megabits of memory which can be assessed using an arbitrary word width. The circuitry to provide access to the configuration bits in this way consists of 3.58 transistors per bit, and results in a routing speed degradation of 11.6% (typical critical path degradation of 5%)