DocumentCode :
3191332
Title :
Improved method for parallel AES-GCM cores using FPGAs
Author :
Abdellatif, Karim M. ; Chotin-Avot, Roselyne ; Mehrez, H.
Author_Institution :
LIP6-SoC Lab., Univ. of Paris VI, Paris, France
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper proposes an efficient method for implementing parallel AES-GCM cores using FPGAs. The proposed method improves the performance of the parallel architecture (Throughput/Slice). Presented architectures can be used for applications which require encryption and authentication with slow changing keys like Virtual Private Networks (VPNs). Our architectures were evaluated using Virtex5 FPGAs. It is shown that the performance of the presented parallel AES-GCM architecture outperforms the previously reported ones.
Keywords :
cryptography; field programmable gate arrays; parallel architectures; Throughput-Slice architiecture; VPN; Virtex5 FPGA; advanced encryption standard; authentication; encryption; field programmable gate arrays; parallel AES-GCM cores; parallel architecture; slow changing keys; virtual private networks; Encryption; Field programmable gate arrays; Hardware; Table lookup; Throughput; Virtual private networks; FPGAs; Parallel AES-GCM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4799-2078-5
Type :
conf
DOI :
10.1109/ReConFig.2013.6732299
Filename :
6732299
Link To Document :
بازگشت