Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance

We apply algorithmic noise-tolerance (ANT) techniques [1] to improve the energy efficiency of DSP circuits implemented on FPGAs. Our approach leverages the programmable power architectural feature in Altera commercial FPGAs that allows internal logic blocks to operate in two modes [2]: high speed or low (leakage) power. We build a main DSP circuit with high utilization of low-power mode blocks, reducing its speed and introducing errors into its output. The errors are subsequently (partially) corrected by a second (smaller) estimation circuit, producing an overall system with higher performance accuracy and lower power than a baseline system built with high-speed logic on its timing-critical paths. We demonstrate a filter implemented in a 40nm commercial FPGA that incorporates ANT and achieves higher SNR using 15% less static power than a traditional filter (without ANT).