DocumentCode :
3191476
Title :
Fault diagnosis and fault model aliasing
Author :
Pomeranz, Irith ; Venkataraman, Srikanth ; Reddy, Sudhakar M.
Author_Institution :
Sch. of ECE, Purdue Univ., W. Lafayette, IN, USA
fYear :
2005
fDate :
11-12 May 2005
Firstpage :
206
Lastpage :
211
Abstract :
During fault diagnosis, the existence of equivalent faults, or faults that are not distinguished by the test set applied to the circuit, can create ambiguity as to the location of a defect. This happens if the circuit-under-test produces a response that matches the circuit response in the presence of two faults in different locations of the circuit. Equivalence between faults of different models, or a test set that does not distinguish two such faults, can increase the ambiguity as to the defect location as well as its type. We refer to this phenomenon as fault model aliasing. We study the extent to which fault model aliasing can be expected to occur under various test sets. We also describe a test generation procedure that can reduce it.
Keywords :
automatic test pattern generation; circuit testing; design for testability; fault diagnosis; circuit-under-test; equivalent faults; fault diagnosis; fault model aliasing; test generation procedure; Circuit faults; Circuit testing; Cities and towns; Delay; Fault diagnosis; Integrated circuit interconnections;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-2365-X
Type :
conf
DOI :
10.1109/ISVLSI.2005.34
Filename :
1430134
Link To Document :
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