Title :
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design
Author :
Ramamoorthy, Saravanan ; Wang, Haibo ; Vrudhula, Sarma
Author_Institution :
Southern Illinois Univ., Carbondale
Abstract :
This paper presents a novel design of address pointer for FIFO memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true single-phase clock, and double- edge-triggering clock scheme. The circuit has low power consumption, is immune to circuit racing conditions and suitable for high-speed operations. Techniques to implement clock gating in pointer circuit design for further reducing power consumption are also discussed. The proposed circuit is implemented with a 65 nm CMOS technology and its performance is compared with previous pointer circuits.
Keywords :
CMOS memory circuits; integrated circuit design; low-power electronics; CMOS technology; FIFO memory design; capacitive load; clock gating implementation; double- edge-triggering clock scheme; double-edge-triggered address pointer circuit; first-in first-out memories; low-power pointer circuit design; pointer clock path; single-phase clock; size 65 nm; CMOS technology; Circuits; Clocks; Design engineering; Energy consumption; Latches; Logic arrays; Random access memory; Read-write memory; Shift registers; FIFO; circuit design; low power; memory;
Conference_Titel :
Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-0-7695-3117-5
DOI :
10.1109/ISQED.2008.4479711
