DocumentCode
3192121
Title
A hierarchical method for wiring congestion prediction
Author
He, Fei ; Song, Xiaoyu ; Cheng, Lerong ; Yang, Guowu ; Tang, Zhiwei ; Gu, Ming ; Sun, Jiaguang
Author_Institution
Sch. of Software, Tsinghua Univ., Beijing, China
fYear
2005
fDate
11-12 May 2005
Firstpage
307
Lastpage
308
Abstract
Interconnect congestion estimation plays an important role in the physical design of integrated circuits. This paper presents a novel probabilistic approach to predicting wiring space in two-dimensional arrays. We propose a hierarchical estimation method to derive approximated upper bounds for wiring space. We use the net density distribution for predicting the routing congestion. Experimental results demonstrate the promising performance of the new approach.
Keywords
integrated circuit design; network analysis; network routing; wiring; integrated circuits design; interconnect congestion estimation; net density distribution; routing congestion prediction; two-dimensional arrays; wiring congestion prediction; wiring space prediction; Computer Society; Partitioning algorithms; Routing; Tree graphs; Upper bound; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.6
Filename
1430167
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