Layout driven synthesis or synthesis driven layout?

ASIC as well as microprocessor design needs require very area efficient, timing driven, power and noise aware synthesis and layout capabilities. However, historically synthesis and layout have been optimized separately. Conventional synthesis aims to reduce the gate count without layout information, as a result, it might reduce logic where it may not result in significant area/power saving or timing benefit. As a consequence, several researchers have focused on integration of synthesis and layout. Some have attempted to provide layout information to synthesis while others have attempted local re-synthesis within the layout. In this tutorial, we review the existing work in the areas of logic and layout interaction. We present a classification of these approaches and their salient features