Title :
A 0.35 μm CMOS 4.8 Gb/s 4:1 multiplexer
Author :
Lu, Jianhua ; Wang, Zhigong ; Tian, Lei ; Tao, Rui ; Chen, HaiTao ; Tingting Xie ; Zhiheng Chen ; Feng, Jun ; Dong, Yi ; Xie, Shizhong
Author_Institution :
Inst. of RF & OE ICs, Southeast Univ., Nanjing, China
fDate :
29 June-1 July 2002
Abstract :
A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 μm CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1×1.05 mm2, and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).
Keywords :
CMOS logic circuits; multiplexing equipment; optical fibre networks; synchronous digital hierarchy; 0.35 micron; 2.488 Gbit/s; 4.8 Gbit/s; 5 V; CMOS multiplexer; SDH; STM-16; optical fiber link; power dissipation; source coupled logic; synchronous digital hierarchy; CMOS logic circuits; CMOS technology; Clocks; High speed optical techniques; Integrated circuit noise; Latches; Logic circuits; Logic design; Multiplexing; Synchronous digital hierarchy;
Conference_Titel :
Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on
Print_ISBN :
0-7803-7547-5
DOI :
10.1109/ICCCAS.2002.1180739
