DocumentCode :
3196068
Title :
Area & delay driven binding algorithm of RTL tech. mapping for heterogeneous FPGAs
Author :
Zhang, Jian ; Bian, Jinian ; Zhou, Qiang
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
fYear :
2008
fDate :
25-27 May 2008
Firstpage :
1231
Lastpage :
1235
Abstract :
Nowadays, FPGA architecture has been improved rapidly, and more and more hard structures are integrated on heterogeneous FPGA chips. RTL technology mapping is one of methods to solve the problem of making use of those hard structures efficiently. However, the traditional RTL mapping tools can not do optimization on the delay on interconnect wires which can not be ignored in the current integrated circuit technology. So this paper focuses on an area and delay trade-off optimization, refers to improved inferring by more complex rules, and make use of simulated annealing algorithm to get a global optimization. The experiment results show our algorithm can give a 10% better optimization on delay.
Keywords :
field programmable gate arrays; integrated circuit technology; simulated annealing; area-delay driven binding algorithm; area-delay trade-off optimization; field programmable gate array architecture; heterogeneous FPGA chip; integrated circuit technology; register transfer level technology mapping; simulated annealing algorithm; Arithmetic; Delay; Electronic design automation and methodology; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuit technology; Laboratories; Libraries; Routing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on
Conference_Location :
Fujian
Print_ISBN :
978-1-4244-2063-6
Electronic_ISBN :
978-1-4244-2064-3
Type :
conf
DOI :
10.1109/ICCCAS.2008.4657990
Filename :
4657990
Link To Document :
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