0.13μm 1.0V–1.5V supply digital blocks for 40-Gb/s optical communication systems

Author

Liang, Bangli ; Kwasniewski, T. ; Wang, Zhigong ; Chen, Dianyong ; Wang, Bo ; Cheng, Dezhong

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, ON

fYear

2008

fDate

25-27 May 2008

Firstpage

1255

Lastpage

1259

Abstract

Low supply digital blocks for OC-768/STM-256 optical communication systems such as 1:2 demultiplexer (DEMUX), 2:1 multiplexer (MUX), 2:1 frequency divider and data decision circuit in 0.13 mum CMOS are presented. All proposed blocks are based on fully differential MOS current-mode logic (CML). Multi-stage output buffers are used to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split resistor (SR) loads are used to boost the bandwidth. High output resistance current sources are employed to achieve flat current source characteristic and allow the designed ICs to operate stably with wide process, voltage and temperature (PVT) variations. The main contribution of this work is that four proposed circuits can work at 40-Gb/s and beyond under a 1 V supply and consume low currents.

Keywords

CMOS integrated circuits; current-mode logic; demultiplexing; frequency dividers; optical communication; CMOS integrated circuit; MOS current-mode logic; bit rate 40 Gbit/s; data decision circuit; demultiplexer; frequency divider; low supply digital blocks; optical communication systems; shunt peaking inductors; size 0.13 mum; split resistor; voltage 1.0 V to 1.5 V; CMOS digital integrated circuits; CMOS logic circuits; Inductors; Multiplexing; Optical buffering; Optical fiber communication; Optical frequency conversion; Resistors; Shunt (electrical); Strontium;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on

Conference_Location

Fujian

Print_ISBN

978-1-4244-2063-6

Electronic_ISBN

978-1-4244-2064-3

Type

conf

DOI

10.1109/ICCCAS.2008.4657995

Filename

4657995