User verify and disturb mechanisms in a 65nm flash FPGA

We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 10⁹ hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.