DocumentCode :
3198589
Title :
Residue-based code for reliable hybrid memories
Author :
Haron, Nor Zaidi ; Hamdioui, Said
Author_Institution :
Comput. Eng. Lab., Delft Univ. of Technol., Delft, Netherlands
fYear :
2009
fDate :
30-31 July 2009
Firstpage :
27
Lastpage :
32
Abstract :
Hybrid memories, structured from scaled CMOS and non-CMOS devices, are novel memory architectures that offer trillion-capacity of data storage. In spite of that, the reliability of such memories is questionable because of (i) imprecise and immature fabrication processes and (ii) unreliable devices. This paper introduces the concept of residue number system (RNS), mainly used in digital signal processing and communication, to the realization of reliable hybrid memories. An error correction code based on RNS to mitigate cluster faults in hybrid memories is proposed; such code is referred to as Six Moduli Redundant Residue Number System (6M-RRNS) code. The experimental results show that 6M-RRNS code can achieve competitive error correction capability as the conventional RRNS (C-RRNS) and Reed-Solomon (RS) codes, yet at lower cost. E.g., for hybrid memories with word size of B = 32 bits, the 6M-RRNS code requires 88 bits to encode the data, whereas C-RRNS and RS codes require 106 and 96 bits, respectively. It means that for a fixed memory size and given correction capability, the total data that can be stored when using 6M-RRNS coding is 20.4% and 9.1% larger as compared with C-RRNS and RS, respectively. Moreover, the speed at which 6M-RRNS decodes the data is 5.6 times faster than when using C-RRNS; hence allowing for higher performance.
Keywords :
CMOS memory circuits; Reed-Solomon codes; error correction codes; integrated circuit reliability; residue number systems; signal processing; Reed-Solomon codes; cluster fault mitigation; data storage; digital signal processing; error correction code; fabrication process; hybrid memories reliability; nonCMOS devices; residue number system; residue-based code; scaled CMOS device; Application software; Automatic control; Automation; Computer aided instruction; Computer science; Computer science education; Control engineering education; Educational technology; Instruments; Military computing; Reliability; error correction codes; hybrid memories; residue number system;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nanoscale Architectures, 2009. NANOARCH '09. IEEE/ACM International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4957-6
Electronic_ISBN :
978-1-4244-4958-3
Type :
conf
DOI :
10.1109/NANOARCH.2009.5226359
Filename :
5226359
Link To Document :
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