Computing with nanoscale memory: Model and architecture

Emerging nanoscale devices hold tremendous potential in terms of integration density, low power operation and switching speed. Unlike CMOS devices, however, majority of these devices are not suitable for implementing cascaded, irregular logic structure. On the other hand, dense and periodic structures of most emerging nanodevices as well as their bi-stable nature make them amenable to large high-density memory array design. Moreover, self-assembly of many nanostructures is efficient for a bottom-up system design flow. Hence, reconfigurable computing paradigms that use memory as underlying computing element, appear promising for these devices. In this paper, first we study nanoscale FPGA, which extends conventional spatial CMOS FPGA architecture using nanoscale memory and interconnect. Next, we focus on a time-multiplexed memory based computing paradigm that employs two-dimensional memory for improved performance, integration density and resource usage.