N-Model Tests for VLSI Circuits

We define N-model tests that target detection of faults belonging to N specified fault models. We provide a method for deriving minimal tests using integer linear programming (ILP) without reducing the individual fault model coverage. Any test sequences, deterministic, random, functional, N-detect, etc., can be minimized for the given set of fault models. Stuck-at, transition, and pseudo stuck-at Iddq faults are used as illustrations. We generate tests using Mentor Graphics FastScan ATPG tool employing a single fault model at a time. A minimized test set for the three fault models is then obtained by solving the proposed combined ILP problem. For s5378 benchmark circuit we achieved about 50% reduction in the number of vectors and 10% reduction in the Iddq current measurements compared to the originally generated tests. We also propose a reduced complexity ILP approximation.